1. Field of Invention
The present invention relates to a damascene manufacturing process. More particularly, the present invention relates to a damascene manufacturing process capable of forming borderless via.
2. Description of Related Art
Conventionally, there are two major methods of fabricating metallic lines. The first method of forming metallic lines includes depositing metallic material over interconnects to form a metallic layer, and then forming a patterned photoresist layer over the metallic layer. Thereafter, using the photoresist pattern as a mask, the metallic layer is etched to form the required metallic lines, and finally an inter-layer dielectric is deposited to cover the metallic lines. The second method of forming metallic lines is a damascene process. In the second method, a dielectric layer is formed over interconnects, and then a patterned photoresist layer is formed over the dielectric layer. Subsequently, an etching technique is used to form a trench in the dielectric layer, and then metallic material is deposited to fill the trench. Finally, a chemical-mechanical polishing (CMP) method is used to remove excess metal and planarize the dielectric layer, thereby completing the damascene process.
As the number of conductive lines in an integrated circuit chip continues to increase, designs having two or more metallic layers are unavoidable. Often, an inter-metal dielectric (IMD) is formed between different metallic layers for isolation purposes.
Conventionally, when via openings are patterned within the dielectric layer, extra area is often reserved around the edges of the via following the design rule. The extra area serves to self-correct any errors resulting from pattern misalignment and therefore avoids problems caused by an increase in contact resistance between the via and the conductive lines below.
However, in modern semiconductor manufacturing, in which the line width of typical devices shrinks to less than 0.25 .mu.m, borderless vias must be used in order to save space. In other words, no extra space is now reserved around the via openings so that the dimensions of each device can be lowered. Without any border area surrounding a via, any misalignment of the via opening with respect to the underlying conductive line will tend to increase contact resistance between the two. An increase in contact resistance will result in an increase in the operating speed of a device, thereby leading to a deterioration of device quality. In some cases, the via opening may be so much out of place that contact between the via and the conductive line below is severed. This will lead to an open circuit condition, causing device malfunction.
FIGS. 1A through 1E are cross-sectional views showing the progression of conventional manufacturing steps necessary for producing a damascene structure that can accommodate a borderless via design.
First, as shown in FIG. 1A, a substrate structure 100 having a planarized surface is first provided. (To simplify the figure, devices within the substrate structure 100 are not drawn.) Then, a dielectric layer 102 is formed over the substrate structure 100. The dielectric layer 102 can be a silicon oxide layer formed using, for example, a chemical vapor deposition method. Thereafter, conventional photolithographic and etching techniques are used to form trenches 104a, 104b and 104c in the dielectric layer 102 to accommodate subsequently formed lower conductive lines. The trenches 104a, 104b and 104c also expose a portion of the substrate structure 100.
Next, as shown in FIG. 1B, a layer of conductive material is deposited over the substrate structure 100 to fill the trenches 104a, 104b and 104c. The conductive material can be copper, aluminum or aluminum/copper alloy, for example. Thereafter, excess conductive material above the dielectric layer 102 is removed using a chemical-mechanical polishing (CMP) method. Consequently, conductive lines 106a, 106b and 106c are formed within the trenches 104a, 104b and 104c, respectively, thereby establishing the first conductive line layer (the lower layer) in the damascene process.
Next, as shown in FIG. 1C, another dielectric layer 112 is deposited over the dielectric layer 102 and the conductive lines 106a, 106b and 106c. The dielectric layer 112 can be a silicon oxide layer formed using, for example, a chemical vapor deposition method. In the subsequent step, the dielectric layer 112 is planarized using a chemical-mechanical polishing operation so that thickness of the dielectric layer 112 is roughly equal to the height of the intended via.
Next, as shown in FIG. 1D, conventional photolithographic and etching processes are used to form a via opening 114 in the dielectric layer 112a. The via opening 114 exposes a portion of the conductive line 106b. However, due to misalignment of the via opening 114 relative to the conductive line 106b, only a portion of the conductive line 106b is exposed. When the misalignment is serious, not even the sidewall of the conductive line 116b is in contact with the via opening 114. Consequently, the subsequently formed via will have little contact area with the conductive line 106b. In some circumstances, an open-circuit condition leading to device malfunction may occur.
Next, as shown in FIG. 1E, a glue/barrier layer 118 conformal to the surface of the via opening 114 is deposited over the substrate structure 100. The glue/barrier layer 118 is used to boost the adhesion between a subsequently deposited conductive layer and other material layers. Thereafter, a conductive layer is deposited over the substrate structure 100. For example, a chemical vapor deposition method is used to deposit a layer of tungsten over the substrate 100. The conductive layer, which is electrically connected with the conductive line 106b, fills the via opening 114 completely. Subsequently, an etching back or a chemical-mechanical polishing operation is carried out to remove excess conductive material above the dielectric layer 112a, thereby forming a via plug 120 within the via opening 114. Due to via misalignment, only a portion of the via plug 120 is in electrical contact with the conductive line 106b.
In the aforementioned process of forming a via opening, contact area between the via plug and the lower conductive line will be reduced as a result of misalignment. Therefore, contact resistance across the via and the conductive line can greatly increase. Hence, the operating speed of the device may be lower and the quality of the device may be compromised. Sometimes, the misalignment may be so severe as to cause an open-circuit condition that may lead to complete malfunction of the device.
In light of the foregoing, there is a need to provide an improved damascene manufacturing process.